Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented

Analog Design Considerations For Independently Driven Double Gate MOSfets And Their Application in a Low-Voltage OTA

Analog Design Considerations For Independently Driven Double Gate MOSfets And Their Application in a Low-Voltage OT

Analog Circuit Design (chapter 5)

Technological advances are mostly guided by performance constraints on digital and radio-frequency circuits. However, an integrated system on chip often involves analog parts. This chapter presents advantages and drawbacks of double gate CMOS technologies in analog design

A 30-to-80MHz simultaneous dual-mode heterodyne oscillator targeting NEMS array gravimetric sensing applications with a 300zg mass resolution

International audienceThe extreme sensitivity of nano electro mechanical system (NEMS) to atomic scale physical variations has led to the breakthrough development of NEMS-based mass spectrometry systems capable of measuring a single molecule [1]. Parallel sensing using thousands of devices will help to circumvent the small effective sensing area while opening new perspectives for applications that require spatial mapping. While the development of NEMS CMOS co-integration technology [2] is of paramount importance to achieve high density sensor arrays (>1000 devices), the readout circuitry capable of tracking NEMS resonator frequency shifts is still the limiting factor for the very large scale integration of individually addressed sensors. Moreover, in order to resolve the mass and position of an adsorbed analyte, single particle mass sensing applications require to track simultaneously and in real time at least two modes of the resonators. This requirement adds complexity to the design of the overall system. To respond to the size, power consumption and resolution constraints linked to NEMS array measurement, we propose a compact heterodyne self-oscillator analog front-end IC which performs 1ms simultaneous $dual-mode$ frequency tracking compatible with a “pixel-based” readout scheme. We report less than 1mA power consumption with a 300zg mass resolution for 26000$\mu$m$^2$ size

A 4-Channel, 7 ns-Delay Tuning Range, 400 fs-Step, 1.8 ps RMS Jitter, Delay Generator Implemented in a 180 nm CMOS Technology

International audienceThis paper discloses the integration, in a 180 nm CMOS technology, of a 4-channel delay generator dedicated to synchronization down to a few ps. The delay generation principle relies on the linear charge of a capacitor triggered by the input pulse. The output pulse generation occurs when the capacitor voltage exceeds a threshold voltage. The delay full scale is automatically set to match the period of the master clock, ranging from 5-7 ns, with the help of an embedded calibration circuit. The delay value is controlled with the help of a 14-bit DAC setting the threshold voltage, which leads to a 400 fs delay step. Among other features, the chip embeds a combination mode of either 2 or 4 channels to output narrow width pulses. The chip is fully compliant with LVDS, LVPECL and CML differential input pulses and outputs LVPECL pulses. The chip has been fully characterized over temperature (0 to 60 °C) and supply voltage (± 10%). The chip is compliant with pulse repetition frequencies up to 20 MHz. The measured INL is 100 LSB and the RMS jitter is 1.8 ps. The power consumption has been measured to 350 mW for 4 active channels

FDSOI for cryoCMOS electronics: device characterization towards compact model

International audienceWe present a status of FDSOI transistors electrical characterization for very low temperature operation. We highlight in particular singular transport and thermal effects occurring at low T. We also present the physical and analytical models associated with various characteristic electrical parameters, paving the way towards cryogenic compact models

Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

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Very Large Scale Integration Optomechanics: a cure for loneliness of NEMS resonators?

International audienceThe first Very Large Scale Integration process with variable shape beam lithography for optomechanical devices is presented. State of the art performance was obtained with silicon microdisk resonators showing 1 million optical quality factors and 10 -17 m.Hz (-1/2) displacement resolution. Single-particle mass spectrometry could be performed with these optomechanical resonators in vacuum. The devices retained high performance when directly immersed in liquid media, allowing for biosensing experiments. These results open the door to large, dense arrays of optomechanical sensors